Cells in conventional dynamic random access memory (DRAM) devices employ a charge storage element, which is generally a storage capacitor. Cells in conventional DRAM have to be periodically refreshed, as the storage capacitor loses charge over time. Additionally, traditional read operations based on charge sharing between a DRAM cell and a bitline cause the charge stored on the storage capacitor in the DRAM cell to be lost. This means that a read operation on a conventional DRAM cell will require reading a value from the cell and then writing the value back to the cell. This is called a “write back” operation.
There are more recent DRAM implementations that do not need the write back operation, but these implementations have additional problems, such as requiring larger silicon area.
Thus, there is a need to provide improved devices for DRAM cells.